A 300MS/s 10bit SAR with loop-embedded input buffer for a photonic system

This work presents a 300MS/s 10bit successive approximation analog to digital converter (SAR-ADC). It is designed in a 180nm technology suitable for co-integration with a photonic system. The ADC employs a loop embedded input buffer to reduce its input capacitance. A current steering DAC is implemented to eliminate kickback to the reference voltage. The proposed topology is independent of the input common mode voltage and thus enables the use of the current steering DAC. The implementation provides a low input capacitance of 386fF and suppresses nonlinearities from the buffer due to input common mode variations.