Design of Integrated Control Circuits for mm-Wave Phased Arrays in 55-nm BiCMOS

This paper presents the design of different control circuits for integrated D-band phased-array transceivers, implemented using a 55-nm BiCMOS process. An SPI slave controller is first presented, which is able to control a bank of sixteen 8-bit registers. The design of an integrated ring-oscillator based clock generator is then described, which oscillates at 44 MHz. Finally, a current-steering 8-bit DAC is presented, which provides a current of 0-1.8 mA with a DNL lower than 0.9 LSB. The DAC can be used to generate bias currents for mm-wave phase shifters and amplifiers, as well as to generate self-test signals at a sampling frequency of up to 100 MSPS. The clock and DAC have been implemented on a test chip that occupies 0.5 mm × 0.4 mm.