Maximal Entropy Reduction Algorithm for SAR ADC Clock Compression

A reduction in the number of comparison cycles leads to power savings for a successive-approximation-register (SAR) analog-to-digital converter (ADC). We establish that the lowest average number of comparison cycles of an SAR ADC approaches the entropy of the ADC output and propose a simple adaptive algorithm that approaches this lower bound. Current SAR ADCs use binary search, which consumes more power than necessary for the nonuniform input distributions commonly found in practice. We refer to an SAR ADC employing such a search algorithm as the maximal entropy reduction ADC (MER ADC). We further comment on the fundamental connection between comparison cycle reduction and source compression.