A 7.1-GHz 0.7-mW Programmable Counter With Fast EOC Generation in 65-nm CMOS

An improved high frequency programmable counter is presented in this brief in realizing divider circuit for frequency synthesizers. The core improvement is based on modification of control architecture in End of Count (EOC) configuration. The overall architecture of the counter shows a speed improvement of more than 24% compared to its predecessor. The design is implemented in 65 nm CMOS technology with silicon occupancy of 42×78 μm
²
, consuming total power of 0.68 mW, at its highest operating frequency of 7.1 GHz in 1.2 V supply. The divider achieves full modulus of 255 with minimum division ratio of 5 at its highest frequency.