Low Power Pre-comparison Configuration Strategy for a Logic-based Binary CAM on FPGA

Content-addressable memory (CAM) is considered an efficient searching technology due to the fact that the output is processed in a deterministic time. However, traditional CAM cannot be implemented on field-programmable gate array (FPGA) owing to the lack of architectural support. Thus, researchers use FPGA resources, i.e., random-access memory, lookup tables, and slice registers to emulate CAM. Unfortunately, FPGA-based CAMs have higher power consumption owing to the concurrent activation of the entire CAM components. Therefore, it is indispensable to design such a strategy that can activate merely the required resources and ultimately reduce the power consumption. In this paper, we present a pre-comparison configuration strategy on a logic-based binary CAM. The proposed CAM has two segments such that the first segment when matched with a few bits of the search key enables the second segment. Thus, it results in power reduction during a search operation. A sample of 64 × 36 of the proposed CAM is implemented on a Xilinx Virtex-6 FPGA. Implementation results show a reduction of 31.27% in power consumption when compared to the latest FPGA-based CAMs without sacrificing the throughput.