Design, modeling and simulation methodology for PCI-X subsystems

This paper describes an electrical design, modeling and simulation methodology for high-speed I/O subsystems utilizing an extension of the peripheral component interface specifications (PCI-X). Actual system configurations and timing specifications are used to describe the design methodology, and to optimize the timing equations for the system level interconnects. The timing budget and noise margin allocation for the various components of the optimization equations are discussed in conjunction with their associated critical design parameters including hot plug requirements.