Signal integrity and design consideration of an MCM for video graphic acceleration

This paper introduces a cost effective MCM for video graphic acceleration of mobile computers. A 1.7 million gate graphic processor IC and two 8 Mbyte DRAM chips are integrated into a 31/spl times/31 mm 4-layer PBGA. Signal integrity analysis and measurement has been done to optimize performance of the present design and a direction for improvement for the next generation product is given thereafter. This study shows that greater consideration given to the MCM application at the IC design stage will maximize MCM performance.