Evaluation of a Chained Systolic Array with High-Speed Links

A paradigm shift toward edge computing infrastructures that prioritize small footprint and scalable/easy-to-estimate performance is increasing. The former improves the yield ratio and the latter eliminates the margin for performance guarantee. Consequently, both of these directions reduce the cost of hardware. In this paper, we propose a chained systolic array that connects small systolic array chips with peer-to-peer AXI interfaces, and evaluate the scalability of several types of topologies such as star, tree and daisy chain with some models implemented on FPGAs connected by aurora links. As a result, we found the star structured 4-chip configuration provides maximum 2.9 × performance of 1-chip configuration, and daisy chain can provide moderate scalability.