Improvement of Cache System Automatic Design Tool for Heterogeneous Multi-Core

Recently, high performance and low energy multi-core processors are required. For this requirement, many researchers of heterogeneous multi-core processors (HMPs) have made various proposals. However, a HMP has diverse processors cores, therefore the design effort of HMPs is seriously heavy. That is known as their main problem when we design HMPs. To solve this problem, we propose FabHetero as an automated design tool for HMPs. FabHetero is a tool set that automatically designs cores, caches, and interconnection networks by using configuration information parameter of generating cache to reduce the design effort of HMPs. However, FabHetero has problems in the cache design part called FabCache. It is a cache automated design tool, but it has dedicated design data in terms of hierarchy. This causes a problem that the design scale and complexity increase explosively when increasing the cache level. This paper proposes a universal cache generating method to reduce the design effort. In our proposed approach, we integrate common parts of different designs across the cache layers.