Study of High-Performance RFIC Designs with Efficient PA Architectures for 5G Networks

The new 5G evolution will remarkably raise the design complexities in handsets and transmission networks. To fulfill the growing demand for high-speed data communication and for enabling the Internet of Things (IoT), a network with high data rates and bandwidth is required. The research is focused on the work to standardize the solutions for network challenges being faced due to high radio frequencies and to enable the highly advanced attributes. The significant amount of research in the Radio Frequency Integrated Circuit (RFIC) is being conducted as the size of an IC is being smaller and its power consumption is very low compared to a discrete circuit. The present study is focused on converting the discrete wireless transceiver circuit into a System on Chip (SOC), where all different components are integrated on to a single chip. The Power amplifier (PA) is a significant part of the wireless transceiver system and consumes a lot of power. Hence the power amplifier becomes an almost integral part of the wireless communication system to study and improve its overall efficiency. In this paper, we present an account of challenges and efficient architectures used for RFIC design suitable for 5G networks.