Drain-Source Synchronous Rectifier Oscillation Mitigation in Light-Load Conditions

The increasing usage of LLC-type dc-dc converters in utility, automotive, and power distribution applications has led to a push for a further increase in the converter's operating load range and efficiency. The secondary-side rectifier remains one of the lossiest areas in the converter, alluring designers to synchronous rectification (SR). One method is drain-source SR for cyclically adaptive, closed loop SR. However, when utilized, a severe current oscillation can be observed. An increase in SR duty cycle results in an increase in conduction time of the SR channel over the body diode. This issue becomes increasingly prevalent due to the usage of wide band-gap MOSFETs with high reverse drops and low sensed signal strength. This results in a current oscillation effect, leading to inconsistent SR operation, output ripple, and high EMI. In this paper, the issue is root caused analyzed. A method of improving drain-source SR for light-load SR operation is proposed. The method is prototyped on an FPGA to alleviate the issue on a 600-V
_in
/340-V
_out
2.5-kW LLC-DCX (DC transformer) power converter.