A Low-Power BFSK Transmitter Architecture for Biomedical Applications

This paper describes a binary frequency shift keying (BFSK) transmitter architecture designed with a technique involving signal generation, mixing, and image rejection for low-power operation. The method enables the coherent generation of the two tones representing the BFSK symbols without changing the phase-locked loop (PLL) output frequency, which relaxes the settling time requirements of the PLL and thus reduces power consumption by design. The architecture allows programmable data rates and channel bandwidths according to application-specific needs. This paper includes analyses of the transmitter signal generation and building blocks. Key design equations are derived to give insights into circuit implementation details. The 480 MHz transmitter was designed and fabricated in a standard 130 nm CMOS technology, and the measurement results provide the first proof-of-concept for the feasibility of this architecture. The transmitter operates around 480 MHz with programmable data rates of 1 Mbps and 10 Mbps. It consumes 170 μW and 180 μW with the two data rates using 0.6 V and 1 V supplies for analog and digital blocks respectively. State-ofthe-art figures of merit for power-efficient BFSK transmission of 170 pJ/bit and 18 pJ/bit are achieved at the data rates of 1 Mbps and 10 Mbps.