The implementation of IEEE Std 1149.1 boundary scan test strategy within a cellular infrastructure production environment

The ever-increasing product complexity and I/O density of new electronic designs has led to the need to implement IEEE Std 1149.1 'Boundary Scan' test techniques within many of the new NSS products. The standard in-circuit test techniques used in Motorola's older product designs were becoming costly to implement and unreliable in a production environment. This paper describes how Motorola NSS developed a IEEE Std 1149.1 test strategy to compliment its other inspection and test techniques. The Motorola IEEE Std 1149.1 test strategy consists of a high level of DFT, starting with component selection with application and implementation notes being generated to aid the design engineers task of implementation. The paper then progresses on to test software and hardware selection, PCB design guidelines and finally Motorola's future direction in a system wide IEEE Std 1149.1 test strategy.