Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy Optimization

Evolution of semiconductor manufacturing technology leads to the rising trend of leakage current and the end of Dennard scaling. At the dark silicon era, aggressive power gating scheme with quantitative management on power-gated hardware resources is required. This paper proposes a novel approach —parallelism scaling — to control static energy on power-gated parallel hardware. This work presents performance-constrained optimization method to power off the greatest possible amount of hardware. As a first trial, this paper examines the idea on VLIW-style architecture exploiting instruction-level parallelism. This paper establishes a theoretical foundation to realize parallelism scaling. The mathematical programming theory includes (1) topological model to control the granularity of program partitioning, (2) optimal partitioning on well-structured control flow graph in polynomial time, and (3) decision support for parallelism through item packing model guided by energy density. Evaluation conducted on EEMBC Denbench benchmark suite shows at least 15% to 53% saving on static energy compared to non-power-gated architecture. Compared to the state-of-art resource management scheme, our approach saves about 20% to 30% energy to meet the same performance demand. The evaluation reveals noteworthy opportunity to save static energy for future dark-silicon architecture design.