Fast and Memory Compact Routing Algorithm for FPGA

Routing is a very critical step in FPGA physical design flow. In this paper, two methods are used to minimize memory utilization and routing time. The first method is modified heap sort which sorts the elements quickly and handles the elements effectively and the second is the modified Routing resource graph (RRG) which is employed to reduce interconnection loops while taking interconnection between all available paths in the routing process. The router using the modified RRG and heap converge faster than the traditional router by using fully expanded RRG.