Power and Area Estimation of Discrete Filters in CMOS Integrated Circuits

The paper proposes a power/area estimation methodology of discrete time filters in CMOS integrated circuits. The difficulty of obtaining an early (at register transfer level design phase) power/area estimate of a filter is many-fold, as estimates depend on (i) target technology, (ii) clocking frequency and (iii) filter complexity (filter topology, length of filter and selected numerical representation of the filter). The estimation methodology consists of (i) VHDL description of the desired discrete time filter using components from PAELib - a previously developed VHDL library suitable for power and area estimation of CMOS digital circuits -, (ii) generation of random data samples and clock signal and (iii) logic simulation. The estimation methodology is demonstrated on three IIR topologies: direct form I/II and lattice. Power and area estimates are obtained for various filter complexities (5 different filter orders and 8 different resolutions) for each topology. From the resulting data, two empirical formula are devised for area and power estimates, in which both are proportional to filter order and resolution and a technology dependent constant. Thus, the power and area estimation - with respect to filter complexity - is reduced to computing a technology dependent constant.