A new framework for static timing analysis, incremental timing refinement, and timing simulation

In this paper we present a framework that enables the computation of tight ranges of signal arrival, transition, and required times for rising and falling transitions at each circuit line, given an input sequence consisting of two partially specified vectors. At one extreme, when the vectors are completely unspecified, this framework becomes identical to static timing analysis (STA). At the other extreme, when the vectors are completely specified, this framework performs timing simulation (TS). Our key motivation for developing this framework was to reduce the amount of search required by a test generator that uses timing information. During test generation for a target fault, values are specified incrementally and this framework enables refinement of timing windows. We demonstrate that this approach significantly improves test generation efficiency. In this mode, the ATPG is said to be performing incremental timing refinement (ITR).