Design Considerations for Si- and Ge-Stacked Nanosheet pMOSFETs Based on Quantum Transport Simulations

Design considerations of vertically stacked horizontal nanosheet (NSH) gate-all-around pMOSFETs are examined at the sub-5-nm technology node using in-house-developed non-equilibrium Green's function (NEGF) quantum ballistic transport simulator. In the individual Si and Ge NSHs, ON-state current and subthreshold swing are evaluated and analyzed for different crystal orientations and various sheet widths. Performance benchmarking of the stacked FET arrays at the iso-footprint is accomplished to explore the roles of sheet configurations further with stack number and sheet spacing changed. It is found that the benefit of the larger effective channel width provided by the wider NSH is always compromised by degraded gate control, especially in the Ge channel. [111] and [100] are shown to be the best transport orientations for individual Si and Ge NSHs, respectively. However, [100] channel vertically confined along [011] shows greater potential for the applications of wider Si and Ge NSHs in the stacked FET array. The process-induced NSH width variation is studied statistically, and it is shown to cause significant performance fluctuations in the stacked array consisting of wide Si or narrow Ge NSHs.