Implementation of High speed, Low PowerModified Vedic Multiplier and Its Application in Lifting based Discrete Wavelet Transform

Implementation of 9/7 Lifting based 2D Discrete Wavelet Transform with the use of high speed and low power Modified Vedic Multiplier is proposed in this paper. Number of adders used in conventional multiplier is reduced in the design of modified Vedic multiplier. The architecture has been designed in VHDL language in Xilinx ISE design suit 14.7. The maximum frequency of the proposed multiplier is 83.012 MHz and power is 60.87 mW for Spartan 3E FPGA. The DWT has power dissipation of 1.161 mW for 180 nm Technology.