Simulink Modeling and Performance Verification of a High Resolution Zoom ADC

This paper presents a Simulink model of a dynamic zoom analog to digital converter (ADC) for use in the field of high resolution sensor readout circuit. The zoom ADC employs a 5-bit asynchronous SAR ADC in the front-end, which dynamically updates the 5-bit DAC references for the following 1-bit second order Sigma-Delta modulator (SDM). Data-weighted averaging (DWA) logic is adopted to alleviate the capacitance mismatch in the 5-bit DAC. The performance of the model is verified by using MATLAB Simulink. The result shows that when the input signal frequency is 150 Hz and the oversampling rate is 1000, the signal-to-noise ratio (SNR) is 127.8 dB, the effective resolution (ENOB) of the system can reach 20.94 bits.