Low-Power, High-Speed Time-Based Subranging ADCs

Time-based analog-to-digital converters (ADCs) are gaining attention as a key technology to solve challenges concerning CMOS scaling. In this paper, our latest research results of low-power, high-speed time-based subranging ADCs are presented. A time-based ADC combining a flash ADC and Vernier time-to-digital converter (TDC) was proposed to achieve a high-speed operation. An 8-bit test chip fabricated with 65-nm CMOS technology demonstrated a high sampling frequency of 900 MHz and a low power consumption of 3.5 mW. A fully-time-based subranging ADC was also proposed to reduce power consumption. Two time-based ADCs were used for both coarse and fine ADCs. An 8-bit test chip fabricated with 65-nm CMOS technology demonstrated a high sampling frequency of 950 MHz and a low power consumption of 2.3 mW.