Implementation of DES Algorithm in New Non-Synchronous Architecture Aiming DPA Robustness

This paper proposes a pipelined architecture of the Data Encryption Standard (DES) Algorithm robust to Differential Power Analysis (DPA) based on globally asynchronous locally synchronous (GALS) project methodology using random clocks. The architecture was prototyped in the Intel Altera© FPGA Cyclone IV and EP4CE115F29C7 device is used as target technology. Robustness is achieved at the cost of only 6.25% average increasing in the use of logic elements. The DPA robustness of the proposal is analyzed through the statistics of the processing time along to 50000 encryptions.