In-Place Power Noise and Signal Waveform Measurements on LVDS Channels in Fan-Out Multiple IC Chip Packaging

Power noise and signal waveforms are in-place measured on low-voltage differential signaling (LVDS) channels within fan-out multiple integrated circuit (IC) chip packaging. A silicon demonstrator in 6.0 mm x 12.0 mm encapsulates a pair of LVDS transceiver chips and power-line noise suppression capacitors which are all interconnected with three level re-distributed metal layers (RDLs). The chip uses a 0.18 μm CMOS technology and integrates an array of LVDS transceivers with per-channel data memory and built-in self-test (BIST) circuitry, along with on-chip waveform monitoring (OCM) circuits as well as power voltage regulators. The in-place waveforms exhibit satisfactorily large signal eye diagrams and small power voltage drops during pseudo-random chip-to-chip data transfer at the clock frequency of 400 MHz. The opportunities are demonstrated to evaluate signal and power integrity over hidden channels in system-level packaging.