Recent Developments in Fine Pitch Wafer-To-Wafer Hybrid Bonding with Copper Interconnect

3D architectures are increasingly making their way into commercial products such as image sensors and 3D memory. While hybrid bonding exists today in wafer-to-wafer (W2W) format in high volume manufacturing, the proliferation of this technology continues to accelerate. A wide range of new products may be considered by leveraging the ability to connect circuit elements fabricated with two different process technologies. For example, some NAND architectures are monolithic 3D devise which are formed using processes with divergent thermal requirements such as the high temperature memory technology and the lower temperature logic. This monolithic approach is the standard today but leads to a final product that is a compromise of the thermal budget constraints. Alternatively, disaggregation of the memory components and the logic components onto separate wafers would allow each technology to be optimized independently with potentially different thermal budgets. Using Cu based hybrid bonding, a fine pitch Cu interconnect may be used to then join the two wafers at temperatures well below 400°C while achieving superior I/O performance within a smaller footprint [1]. Direct Bond Interconnect (DBI
^®
) technology, is a low temperature hybrid bonding process that forms a dielectric-to-dielectric bond at room temperature and a metal-to-metal bond at the appropriately designed temperature. It is the key enabling technology for advanced products because of its unique ability to bond wafers at low temperature and to successfully bond pads ranging from 1.9 μm to 15 μm diameter. The corresponding pitches range from 3.8 μm to 40 um. Generally, a low temperature anneal process of 150-400°C can be achieved. The all-Cu interconnect across the bond interface provides good electrical performance and enhanced reliability. [2] This paper presents bonding and electrical yield results with a test vehicle design that demonstrates high-density, fine pitch bonding with high-yield. The test vehicle consists of daisy chain test patterns with 4 μm bonding pitch with 115k links and covers a bond area of 3.61 mm
²
. The process flow enables high throughput processing with room temperature bonding and post-bond batch anneal. The process shows minimum electrical yield greater than 98% across all wafers. Longer chains of 500k links with a 3 μm diameter pad with a 10 μm pitch show similar yields. Temperature cycling and autoclave tests of the 3 μm diameter pad test structures showed a robust Cu/Cu interconnection and superior reliability performance.