Time-Skew Estimation for Random Sampling Sequence Time-Interleaved ADCs

This brief proposes a closed-loop architecture which performs background calibration of time-skew mismatch in time-interleaved ADCs (TIADCs). The proposed scheme is tailored to work with the use of a random sampling sequence (RSS) which can provide an improvement in the SFDR without incurring a penalty in the SNDR. The calibration algorithm places some constraints on the random sampling sequence, which are satisfied via a proposed sequence generation algorithm based on a linear-feedback shift register (LFSR). We also show how the timing reference can be selected so as to reduce the requirements of the time-skew correction circuit, and we demonstrate the resulting production yield improvements. The proposed algorithm was synthesized for a TIADC composed of 9 sub-ADCs having an aggregated sampling rate of 2.4GS/sec in a 28nm process; the design occupies 0.014mm
²
and consumes 2.93mW. We demonstrate that the proposed algorithm successfully compensates the time-skew mismatch, allowing to achieve SFDR above 100dB.