Thermal Stress Reduction for DC-link Capacitors of Three-phase VSI with Multiple PWM Switching Patterns

This paper demonstrates the thermal stress reduction for the DC-link capacitors with multiple PWM strategies. An optimized positioning of the gate pulse reduces the DC-link capacitor current. The capacitor current reduction space vector PWM (SVPWM) strategies reduces the film capacitor core temperature by a maximum of 9.0°C compared to those obtained with the conventional strategies, whereas the maximum allowable temperature of the film capacitor is 105°C. The carrier-based PWM approaches also reduce the thermal stress; however, the reduction amount is not as large as the SVPWM approach. In addition to the trade-off between the implementation requirement and the reduction effect on the capacitor current, the analytical and experimental results confirm that there is a trade-off between the improved capacitor current harmonics and the worsened load current harmonics.