An Efficient Pipelined Architecture for Superconducting Single Flux Quantum Logic Circuits Utilizing Dual Clocks

In standard single flux quantum (SFQ) logic circuits, it is required to insert path balancing D-flip-flops (DFFs) to guarantee correct circuit operation. DFF insertion should be done in a way that any path from a primary input to a primary output has the same length in terms of the clocked element count. This is known as full path balancing (FPB) method. The FPB method usually requires insertion of many path balancing DFFs that can be even more than the actual gate count in the original circuit. This significantly increases the chip area, lowers the local clock frequency, and increases both static and dynamic power dissipation. This article presents an architecture for realizing SFQ circuits which removes all path balancing DFFs, resulting in a huge reduction in total area, node and Josephson junction count, and power consumption. The drawback is a degradation of the peak throughput of the circuit, which can be overcome by performing partial path balancing in the circuit, thereby recovering the circuit throughput by adding some path balancing DFFs.