Simulation of 2-bit SONOS Nonvolatile Semiconductor Memory Cell

In this paper, simulation of 2-bit SONOS (silicon-oxide-nitride-oxide-silicon) nonvolatile memory is perfomed. This single device cell has a two physical bit storage capability. Moreover, The method is based on characterization of localized trapped-charge in the nitride layer. Programming is performed by channel hot electron injection. Furthermore, The read methodology is based on drain induced barrier lowering (DIBL) mechanism and very sensitive to the location of trapped charge in storage layer. In this design sentaurus Tcad tool in 130nm technology is used.