A 5-Gb/s decision circuit fabricated in a 1.5- mu m super-self-aligned silicon bipolar IC technology

The design and experimental measurements on a clocked decision circuit for optical communication applications are reviewed. The circuit, fabricated in a 1.5- mu m super-self-aligned silicon bipolar technology, yields a bit-error rate (BER) <10/sup -9/ at a bit rate of 5 Gb/s. At 2.5 Gb/s the small signal input data sensitivity is 10 mV, the clock timing margin is 320 ps (288 degrees phase margin), the output eye-pattern opening is 300 ps (270 degrees phase margin), and the rise/fall times are about 100 ps.<
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