An All-Digital Duty-Cycle Corrector for Parallel High-Speed I/O Links

In this work, an all-digital duty-cycle corrector (DCC) based on the combination of a CML2CMOS converter and a 5 bit duty-cycle adjuster is presented. The design is optimized for the application in parallel high-speed I/O links and provides a wide input duty-cycle range of up to 15 %-85%. The duty-cycle detector incorporates a fully synthesized phase-to-digital converter based on asynchronous sampling. The option to measure the duty-cycle after a clock or data off-chip driver can reduce the overall duty-cycle error of a high-speed transmitter by including the influence of the driver. The proposed DCC can be operated at 2–5 GHz and occupies only 0.0037 mm
²
in a 65 nm CMOS process with a power efficiency of 0.48mW/GHz. The measured RMS and peak-to-peak jitter is 1.87 ps and 12.97 ps, respectively, and the maximum duty-cycle error is 0.8 %.