Design of Asynchronous CNN Circuits on Commercial FPGA from Synchronous CNN Circuits

To accelerate performance, Convolutional Neural Networks (CNNs) are frequently used in Field Programmable Gate Arrays (FPGAs). In this paper, to reduce the power consumption of CNN circuits, we propose a design method to design asynchronous CNN circuits on commercial FPGAs. First, the proposed method converts Register Transfer Level (RTL) models of synchronous CNN circuits to RTL models of asynchronous CNN circuits. Then, the proposed method designs asynchronous CNN circuits using a commercial FPGA design environment. In the experiment, we designed an asynchronous CNN circuit and evaluated the performance. Compared to the synchronous counterpart, the asynchronous CNN circuit consumed about 2.3% less energy.