A Real-Time Flexible Telecommunication Decoding Architecture Using FPGA Partial Reconfiguration

Modern telecommunication decoding schemes, leading to high computational complexity and power consumption, are weakening the feasibility of real-time applications. In this brief, a real-time reconfigurable decoding architecture is introduced to alleviate the contradiction mentioned above. The proposed architecture is partially reconfigurable on the fly so that different decoding schemes can be deployed onto merely one physical partition of reconfigurable hardware and be switched with another without significant penalty on timing and complexity. The decoding system is implemented on an FPGA evaluation board and the experiment result shows that our approach renders ple decoding schemes implemented in one system with feasibility, simplicity and power-saving ability. By adopting our architecture and the development flow, a three-LDPC-code decoder is implemented. Moreover, nearly 50% savings on hardware logic and milli-second-level real-time switching speed for decoders are both achieved.