Failure Probability Analysis of Two Novel Redundant Transistor Structures

As Moore’s Law scaling down to nanometer era, process variability, transistor defects and space radiation effects have made hard errors much more common than ever before. Unlike soft errors, hard errors can do permanent damage to integrated circuits. This paper analyzes the failure probabilities of several redundant transistor structures in detail. Massive simulations and calculations indicate the proposed structures shows advantages in area, power consumption and reliability compared with former designs, especially when the incidences of two types of transistor faults are unequal. Besides, this paper gives the failure probability of a NAND gate, described by the probability of a defective transistor. The deduced formula reveals a nonlinear relation between failure probability of a NAND gate and that of a transistor.