Charge Collection of twin well PN junction in 65 nm CMOS Inverter

The charge collection of PN junction between wells will obviously extend the SET (single event transient) pulse width due to the accumulation of excess carrier via drift and diffuse process. The results of the heavy Ion irradiation experiments show that different n-well structures influence the SET pulse width. Further TCAD simulations were carried out to verify the PN junction between wells cause parasitic PNP bipolar transistor open for longer time. Results show that junction formed by p-well and n-well lead to worse recovery feature of 65nm CMOS inverter.