An FPGA-based SRAM Single Event Multiple-bit Upset Detection Method

This paper analyzes the designing of the existing SRAM single event upset (SEU) detection system and points out that the upset statistical method based on PC software is the system performance bottleneck. The paper aims at the bottleneck and presents a single event multiple-bit upset (MBU) detection system based on FPGA logic circuit, which has high detection speed, high data integrity, etc.