Characterization of On-Chip Interconnects: Case Study in 28 nm CMOS Technology

Performance of a high-speed network on a chip is mainly affected by the performance of the global on-chip interconnects. This paper investigates a point-to-point transmission line interconnect to address the performance limitations due to the scaling problems of on-chip global interconnects in new CMOS technologies. A brief explanation is given about the basic properties of the transmission lines that should be considered. Moreover, the design methodology is given for designing the on-chip interconnect and understanding its behavior. Based on the different transmission line geometry, 3D EM simulations are done and S-parameters are carried out to analyze the effects of the different metal layers, width of the signal line, and space to shield layers of the interconnect. This results in a systematic understanding of the design of the on-chip interconnect and its performance dependence on various parameters. Finally, a 5 mm length on-chip lossy transmission line with serpentine shape and shielding layers is implemented in 8-metal-layer 28 nm CMOS standard technology.