Design and Verification of Wishbone I2C Master Device

As the complications in designing of chip is increasing through the decade, design engineers have taken effort to create and verify the functionality of the design. An SOC chip usually contains a plethora of IP cores which start transactions to exchange information utilizing on-chip buses. As the VLSI process technology is advancing at a faster pace, the frequency and the quantity of the data shared amidst the IP cores has risen gradually. Therefore, the capability of on-chip buses to handle the huge quantity of data traffic becomes a prevalent reason for the overall performance. In this project major task and the main intention is to verify functionality of Wishbone target and I2C master core interface. The core reason behind choosing this interface is Wishbone is on-chip and parallel bus,I2C is serial and board level bus therefore this interface could be utilized for the FPGA’S as the design is reusable. . In this paper we are exactly concentrating on building and verifying the design utilizing different test-cases. According to the RTL code written, the entire analysis which includes the design and verification is performed to verify the code functionality, therefore to carry out the same one has to create an arena which can generate / sense signals which are going or coming from / to the given bridge which is our DUV (Design Under Verification). The verification is done using system verilog verification environment.