Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part I: Accurate and Computationally Efficient Modeling

Resistive switching memory (RSM) shows potentials for high-capacity storage because of its simple cell structure, small footprint, and good scalability. This two-part article discusses how to implement ultrahigh-density (~terabits) storage with RSM covering design considerations from device to memory array architecture. In Part I of this two-part article, an accurate and computationally efficient model is developed to study 3-D vertical RSM (VRSM). In this article, we use 3-D VRSM with a hexagon-patterned pillar layout (3-D hexagon VRSM) as an example to elaborate our approach. Using the parasitic resistance extracted from physics-based 2-D field solver as the reference, we develop a lumped resistor network for SPICE simulation to accurately capture all leakage currents of the array. This full resistor network is further simplified to a reduced network to achieve high computational efficiency and maintain the full network accuracy (with a relative error <; 2%). Without this simplification, practical memory array sizes cannot be simulated efficiently. The interplay between the memory cell resistance values and selector nonlinearity (NL) on the maximum array size and the write/read margins under the worst case scenarios is discussed. Large memory cell resistance (low-resistance states ≥100 k) with enough NL (~10³) from the selector is recommended for successful write/read operations in a single 3-D hexagonal VRSM array of megabit scale.