HDML: compiled VHDL in XML

Communication between designers and tools is a necessity and plays a significant role in productivity and time to market. XML, as an emerging standard, has proved to be a very suitable format for exchanging data on network and between applications. In addition, there are many public-domain tools for manipulating data in XML format regardless of what that data represents. HDML (Hardware Description Markup Language) is a new model for representing compiled data from original VHDL code in XML format. In addition to benefiting from XML advantages, HDML also develops a powerful mechanism for rule checking on a compiled design model. Although, the model does not depend on a specific data structure, we have used a revised version of ATRE/CE for developing an analyzer for converting VHDL to HDML. To illustrate the capabilities of HDML, this paper discusses an example application of our XML based intermediate format, which is typical of many other potential applications. This specific application checks syntax and semantics of an input VHDL code for synthesis and we refer to is as the synthesizability rule checker.