Modeling Techniques for Faster Verification of a Time to Digital Converter System-on-Chip Design

In this paper, we present the modeling techniques used for faster simulation and verification of a time to digital converter (TDC) IC, designed for India-based Neutrino Observatory. The mixed signal implementation of the TDC necessitates rigorous verification of the interaction between the digital and analog blocks. The paper discusses how the major analog circuits were reduced to logic level models in Verilog while retaining the required accuracy for faster top-level simulations. In order to facilitate quicker verification of the simulation results, a behavioral-level TDC model which has minimal common algorithm with the implemented system is developed. This model is used within self-checking testbenches to create a reference against which simulation results are validated. These modeling techniques enabled the automation of the verification process, thereby reducing the design verification time significantly. The simulation and verification of 600 test cases were completed in less than 9 hours, whereas the mixed signal simulation for a single test case would have taken several days to complete.