Implementation of a Modified Global Routing Algorithm on a High-throughput Parallel Environment

Complexity and productivity of modern day Integrated Circuits (ICs) have increased due to aggressive transistor scaling. The exponential increase of circuit complexity brings a tremendous challenge to all phases in the design flow of ICs especially routing. Global routing is the most time consuming phase in physical design flow. As it needs to be performed multiple times, performance improvement in terms of time and solution is of prime importance. Several techniques have been developed including Rip-up and Reroute(RRR) and parallelization to achieve such goals. The work reported in this paper is executed on Julia which is configured for parallelism. Julia is a high-level, dynamic language with an easy-to-use multiprocessor mechanism and much less code complexity. Techniques proposed in this paper is implemented in Julia with an average 2x speed-up obtained on a quad-core processor compared to single core processing. Also, the proposed approach balances the load and reduces the overload on the processors.