Temperature and Gate Leakage Influence on the Z2-FET Memory Operation

Advanced 28 nm node FD-SOI Z
²
-FETs with thin top-gate insulator are characterized as capacitor-less DRAM cells. Experimental and 2D-TCAD results demonstrate that the memory window shifts while the retention time is reduced as the front-gate geometry is down-scaled or temperature is increased. The degradation of the memory performance can be attributed to gate tunneling current and Generation-Recombination mechanisms. The low-frequency noise and the front-gate leakage current have been experimentally studied, corroborating trap-assisted tunneling as the main degrading contributor under memory operation.