Record GmSAT/SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation

This article reports Si-passivated Ge nFinFETs with significantly improved Gm
_SAT
/SS
_SAT
and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high-k last process. SiO
₂
dummy gate oxide (DGO) deposition on Ge fin is shown to form (Si
_x
)Ge
_1-x
O
_y
, which is, compared to a pure SiO
₂
, more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced D
_IT
, and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum V
_OV
of 0.13 V, the best Gm
_SAT
/SS
_SAT
of 5.4 is achieved, which is today's record value among the sub-100-nm-L
_g
n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack.