Design and Optimization of 1.2-kV SiC Planar Inversion MOSFET Using Split Dummy Gate Concept for High-Frequency Applications

The gate architecture of a 1.2-kV SiC planar MOSFET is engineered to obtain the improved high-frequency figure of merit (HF-FOM) over the split-gate (SG) and planar-gate topology. In this article, we propose a device using the split dummy gate (SDG), which is in short with the source contact at zero potential. The device has a lower reverse transfer/feedback capacitance (C
_rss
or C
_gd
) due to the formation of depletion width under SDG and lower gate-to-drain charge (Q
_gd
) due to reduced overlap with the substrate leading to excellent HF-FOM(R
_on,sp
× C
_gd
and R
_on,sp
× Q
_gd
). The essential electrical characteristics (such as Ron,sp, breakdown voltage (BV), and V
_th
) remain almost similar compared to the device without the dummy gate. The obtained HF-FOM(R
_on,sp
× Q
_gd
) is 28.7× and 186× lower compared to the device with SG and planar-gate topology, respectively.Using calibrated Sentaurus TCAD simulations, the proposed SDG MOSFET has shown negligible Miller plateau (Q
_gd
), reduced crowding of the electric field at the SG corner, and improved turn-on/off characteristics with a reduction in switching energies.