Jitter Estimation in a CMOS Tapered Buffer for an Application of Clock Distribution Network

This paper presents an analysis and estimation of timing error due to the power supply noise for a five-stage CMOS tapered buffer used in the clock distribution network for the application of successive approximation register (SAR). The complete design is simulated in standard 28 nm CMOS technology with the supply voltage of 0.9 V. The closed-form expressions for time interval error have been derived using the matrix inversion method, considering the impact of deterministic supply noise. The results obtained from a slope-based semianalytical jitter estimation method are compared with the SPICE based simulations. The results show a good agreement with a maximum error of 4 %.