Novel gate-grounded NMOS Triggered Device Structures for FD-SOI ESD Protection

The novel gate-grounded NMOS (gg-NMOS) triggered device structures are proposed for the full-depleted silicon-on-isolation (FD-SOI) electrostatic discharge (ESD) protection, which can be manufactured in an advanced 22-nm FD-SOI process. The gg-NMOS structures are realized in the silicon film and used as a triggering element to inject electron current to switch on bipolar junction transistors (BJTs) or silicon-controlled rectifiers (SCRs) under the BOX layer. The electron injection can be adjusted by changing the P-well/N-well contact position and the channel length of the gg-NMOS. Therefore, the novel structures can have the adjustable triggering voltage to meet different ESD design window. Besides, they are able to achieve a high second breakdown current, which is similar to that in the bulk process.