Establishment of ESD Generator Model for Transient Susceptibility Analysis from Chip to System Level

There is a growing awareness in the electronics manufacturer that system level ESD robustness is an important requirement for reliable products. System level ESD testing is today applied to a wider range of products than ever before. Designing ESD robust systems can be very challenging, especially for systems which integrate advanced technology integrated circuit (IC) components. While IC level ESD design and the necessary protection levels are well understood with reliability test from CDM or HBM model, system ESD protection strategy and design efficiency have only been dealt with in an ad hoc manner. We wish to explore realistic system or chip ESD protection requirements and strategies for normal operating IC chip or system, and therefore we have to establish the realistic ESD generator model to be incorporated with chip or system under investigation. Many of the most severe system level ESD design problems can be then traced to the affected location of system or chip with analyzing the residual ESD stress after injection and propagation. With this help, we can then adopt a consolidated approach to system level ESD design, and validate future success in building ESD robust systems through simulation in advance.