A Novel Gate-Coupled NMOS (gcNMOS) for FD-SOI ESD Protection

A novel gate-coupled NMOS (gcNMOS) structure for electrostatic discharge (ESD) protection is proposed in this paper, which can be realized in an advanced 22-nm full-depleted silicon-on-isolation (FD-SOI) technology. The triggering voltage of the proposed device structure can be adjusted to meet different ESD requirements. This innovative configuration is characterized by the resistance used to connect the gate and the ground as well as the double-well under the buried oxide (BOX), which can alter the gate potential and the electron density of the channel. Compared with previous structures, the triggering voltage of the proposed structure can range in a large scale without additional silicon consumption.