Novel Control Unit Design for a High-Speed SHA-3 Architecture

This paper presents a control unit design for improving the throughput of SHA3-256 architecture. The Iterative data path design is employed to process multi-block messages, which makes the design functional for any input size. A higher throughput is achieved by reducing the number of control signals in the critical path, and optimizing the counter which generates the memory address and affects the maximum operating frequency. The synchronization problems caused by this approach between the generated Hash and its corresponding Valid signal, are overcome by the Synchronizer. The proposal exhibits 920 Mbps higher throughput, i.e. a 7% improvement over state of the art.