Design of A 52.5 dB Neural Amplifier with Noise-Power Trade-off

An accelerating interest in neuromodulation and brain-machine interfacing has resulted in the development of multi-channel neural signal recording systems over the past few decades. A critical part of the acquisition system is the analog front-end, which includes the neural amplifier with low-power and low-noise configuration in the sub-Hz operating frequency. This paper presents a neural signal recording amplifier that is capable of amplifying signals in the sub-Hz to kHz frequency range. The amplifier is designed in standard 0.5 μm CMOS process with a fully-differential architecture. The proposed operational transconductance amplifier (OTA) uses two-stage topology and a capacitive-resistive feedback technique to have the lower and the higher cut-off frequency as 0.125 Hz and 1.258 kHz respectively to record the low-frequency neural signals. It achieves a common-mode rejection ratio (CMRR) of 97.1 dB, a power supply rejection ratio (PSRR) of 84.4 dB. The amplifier achieves a mid-band gain of 52.53 dB with the total power consumption of 4.12 μW with a supply voltage of 3.3 V by making the transistors operate in the sub-threshold region. The amplifier is designed taking into account the noise-power trade-off, and the input-referred noise of the amplifier is found to be 3.16 μV
_rms
over a bandwidth of 0.1 Hz- 5 kHz. The prototype single channel amplifier has an active die area of 0.28 mm
²
. The overall performance metrics of gain, power consumption and the noise performance of the proposed amplifier make it a good choice for neural signal recording applications.